preliminary 3-mbit (128k x 24) static ram cy7c1024dv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-08353 rev. *a revised september 4, 2006 features ?high speed ?t aa = 8 ns ? low active power ?i cc = 185 ma @ 8 ns ? low cmos standby power ?i sb2 = 25 ma ? operating voltages of 3.3 0.3v ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 , ce 2 and ce 3 features ? available in pb-free standard 119-ball pbga functional description the cy7c1024dv33 is a high-performance cmos static ram organized as 128k words by 24 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. to write to the device, enable the chip (ce 1 low, ce 2 high and ce 3 low) while forcing the write enable (we ) input low. to read from the device, enable the chip by taking ce 1 low ce 2 high and ce 3 low while forcing the output enable (oe ) low and the write enable (we ) high. see the truth table at the back of this data sheet for a complete description of read and write modes. the 24 i/o pins (i/o 0 ?i/o 23 ) are placed in a high-impedance state when all the chip selects are high or when the output enable (oe ) is high during a read mode. for further details, refer to the truth table of this data sheet. selection guide ?8 unit maximum access time 8 ns maximum operating current 185 ma maximum cmos standby current 25 ma functional block diagram 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 128k x 24 array a 0 a 12 a 14 a 13 a a a 10 a 11 oe i/o 0 ?i/o 23 ce 1 , ce 2 , ce 3 we a 9 control logic [+] feedback [+] feedback
preliminary cy7c1024dv33 document #: 001-08353 rev. *a page 2 of 8 pin configurations [1] 119 pbga top view 1234567 a ncaaaaanc b nc a a ce 1 aanc c i/o 12 nc ce 2 nc ce 3 nc i/o 0 d i/o 13 v dd v ss v ss v ss v dd i/o 1 e i/o 14 v ss v dd v ss v dd v ss i/o 2 f i/o 15 v dd v ss v ss v ss v dd i/o 3 g i/o 16 v ss v dd v ss v dd v ss i/o 4 h i/o 17 v dd v ss v ss v ss v dd i/o 5 j nc v ss v dd v ss v dd v ss nc k i/o 18 v dd v ss v ss v ss v dd i/o 6 l i/o 19 v ss v dd v ss v dd v ss i/o 7 m i/o 20 v dd v ss v ss v ss v dd i/o 8 n i/o 21 v ss v dd v ss v dd v ss i/o 9 p i/o 22 v dd v ss v ss v ss v dd i/o 10 r i/o 23 nc nc nc nc nc i/o 11 t nc a a we aanc u nc a a oe aanc note: 1. nc pins are not connected on the die [+] feedback [+] feedback
preliminary cy7c1024dv33 document #: 001-08353 rev. *a page 3 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd [2] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] ....................................?0.5v to v cc + 0.5v dc input voltage [2] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .... ........... .............. ......>2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c3.3v 0.3v dc electrical characteristics over the operating range parameter description test conditions [7] ?8 unit min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il [2] input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc i out = 0 ma cmos levels 185 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 30 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 25 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8 pf c out i/o capacitance 10 pf thermal resistance [3] parameter description test conditions pbga unit ja thermal resistance (junction to ambient) st ill air, soldered on a 3 4.5 inch, four-layer printed circuit board tbd c/w jc thermal resistance (junction to case) tbd c/w ac test loads and waveforms [4] 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf including jig and scope (b) r1 317 ? r2 351 ? rise time > 1 v/ns fall time: > 1 v/ns (c) 50 ? notes: 2. v il (min.) = ?2.0v and v ih (max) = v cc + 2v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters. 4. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). 100 s (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. (a) output z 0 = 50 ? v th = 1.5v 30 pf* * capacitive load consists of all components of the test environment. [+] feedback [+] feedback
preliminary cy7c1024dv33 document #: 001-08353 rev. *a page 4 of 8 ac switching characteristics over the operating range [5] parameter description ?8 unit min. max. read cycle t power [6] v cc (typical) to the first access 100 s t rc read cycle time 8 ns t aa address to data valid 8 ns t oha data hold from address change 3 ns t ace ce active low to data valid [7] 8ns t doe oe low to data valid 5 ns t lzoe oe low to low-z [8] 1ns t hzoe oe high to high-z [8] 5ns t lzce ce active low to low-z [7, 8] 3ns t hzce ce deselect high to high-z [7, 8] 5ns t pu ce active low to power-up [7, 9] 0ns t pd ce deselect high to power-down [7, 9] 8ns write cycle [10, 11] t wc write cycle time 8 ns t sce ce active low to write end [7] 6ns t aw address set-up to write end 6 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 6 ns t sd data set-up to write end 5 ns t hd data hold from write end 0 ns t lzwe we high to low-z [8] 3ns t hzwe we low to high-z [8] 5ns notes: 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. test conditions for the read cycle use output loading as shown in part a) of t he ac test loads, unless specified otherwise. 6. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access is performed. 7. ce refers to a combination of ce 1 , ce 2 , and ce 3 . ce is active low when ce 1 is low and ce 2 is high and ce 3 is low. ce is deselect high when ce 1 is high or ce 2 is low or ce 3 is high 8. t hzoe , t hzce , t hzwe , and t lzoe , t lzce , t lzwe , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 9. these parameters are guaranteed by design and are not tested. 10. the internal write time of the memory is defined by the overlap of ce 1 and ce 2 and ce 3 low and we low. the chip enables must be active and we must be low to initiate a write, and the transition of any of these si gnals can terminate the write. the input data set-up and hold tim ing should be referenced to the leading edge of the signal that terminates the write. 11. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
preliminary cy7c1024dv33 document #: 001-08353 rev. *a page 5 of 8 data retention characteristics (over the operating range) parameter description cond itions min. typ. max. unit v dr v cc for data retention 2 v i ccdr data retention current v cc = 2v , ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v 25 ma t cdr [3] chip deselect to data retention time 0 ns t r [12] operation recovery time t rc ns data retention waveform 3v 3v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms read cycle no. 1 [13, 15] read cycle no. 2 (oe controlled) [14, 15, 16] notes: 12. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s 13. device is continuously selected. oe , ce = v il . 14. ce refers to a combination of ce 1 , ce 2 , and ce 3 . ce is active low when ce 1 low and ce 2 high and ce 3 low. 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current [+] feedback [+] feedback
preliminary cy7c1024dv33 document #: 001-08353 rev. *a page 6 of 8 write cycle no. 1 (ce controlled) [14, 17, 18] write cycle no. 2 (we controlled, oe high during write) [14, 17, 18] write cycle no. 3 (we controlled, oe low) [14, 18] notes: 17. data i/o is high impedance if oe = v ih . 18. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 19. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 19 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 19 [+] feedback [+] feedback
preliminary cy7c1024dv33 document #: 001-08353 rev. *a page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram all product and company names mentio ned in this document may be the tr ademarks of their respective holders. truth table ce 1 ce 2 ce 3 oe we i/o 0 ?i/o 23 mode power hxxxxhigh-z power-down standby (i sb ) x l x x x high-z power-down standby (i sb ) x x h x x high-z power-down standby (i sb ) l h l l h full data out read active (i cc ) l h l x l full data in write active (i cc ) l h l h h high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 8 CY7C1024DV33-8BGXC 51-85115 119-ball plastic ball grid array (14 x 22 x 2.4 mm) (pb-free) commercial 51-85115-*b 119-ball pbga (14 x 22 x 2.4 mm) (51-85115) [+] feedback [+] feedback
preliminary cy7c1024dv33 document #: 001-08353 rev. *a page 8 of 8 document history page document title: cy7c1024dv33 3-mbit (128k x 24) static ram document number: 001-08353 rev. ecn no. issue date orig. of change description of change ** 469517 see ecn nxr new data sheet *a 499604 see ecn nxr added note# 1 for nc pins changed i cc spec from 150 ma to 185 ma updated test condition for i cc in dc electrical characteristics table added note for t ace , t lzce , t hzce , t pu , t pd , t sce in ac switching characteristics table on page# 4 [+] feedback [+] feedback
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